ML-Assisted VminBinning with Multiple Guard Bands for Low Power Consumption
Journal
Proceedings - International Test Conference
Journal Volume
2022-September
ISBN
9781665462709
Date Issued
2022-01-01
Author(s)
Abstract
A two-phase chip performance prediction flow is presented to avoid severe costumer return, reduce power consumption, and mitigate yield loss. In phase I, we first predict the initial value of minimum operating voltage (Vmin). In phase II, we predict the bin for each chip in order to apply different guard bands. Experiments on 851 advanced 7nm mobile chips show that predicted Vmin is larger than actual Vmin for all chips to avoid customer return. Also, power consumption is reduced by 2.69%. Yield loss is mitigated by up to 5.05% when our Vmin requirement is 1.20 scaled Vmin. To implement our flow, we only need to spend a little more runtime compared to the conventional flow. While the runtime of our flow is still short, we can save the long time of measuring Vmin for every chip.
Subjects
Chip performance prediction | Multiple binning | Process variation
SDGs
Type
conference paper