SRAM with Oxide Semiconductor Pull-Down Transistors on the Backside Enabling Full-Node PPA Improvement
Journal
IEEE Electron Device Letters
Start Page
1
End Page
1
ISSN
0741-3106
1558-0563
Date Issued
2024
Author(s)
Abstract
The 6T SRAM bitcell, consisting of four pFETs on the same tier and two oxide-semiconductor pull-down transistors stacked on the backside, can achieve 17% power reduction, 32% performance enhancement, and 42% area reduction as compared to one-tier SRAM bitcell. With the high strength ratio of the pass-gate transistors to the pull-down transistors, near-threshold-voltage write reduces the minimum operating voltage.
SDGs
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Type
journal article