A highly integrated class-D amplifier using driver delay hysteresis control
Journal
2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012
Date Issued
2012
Author(s)
Abstract
In this paper, a closed-loop class-D amplifier (CDA) simplifying circuit implementation on conventional hysteresis control is proposed. The functionality of hysteresis control is realized by comparator in conjunction with MOSFET propagation delay. The switching frequency variation is reduced by means of unmatched rising and falling edge delays. The prototype CDA chip is fabricated in 0.35-m CMOS process and its active area is 0.2 mm 2. The measurement results show that THD+N ratio is flat between 20 Hz and 20 kHz with all values below 0.03%. PSRR and SNR are 64 dB and 80 dB, respectively. © 2012 IEEE.
SDGs
Type
conference paper