Memory Management System in Stochastic ARM1136JF-S
Date Issued
2014
Date
2014
Author(s)
Liao, Wei-Tse
Abstract
Stochastic processors are designed to handle non-deterministic errors. The robustness issue is the most important design consideration. No error is allowed in an OS-based processor. To achieve an error-free processor, error-resilience circuits are necessary. In addition to the robustness issue, the performance of a memory system is another crucial design consideration. Level-one Cache Controller plays an important role to make the memory system keep up with the high frequency of the processor. Given a high-performance pipeline processor and a cache memory capacity limitation, reducing miss penalty seems to be a possible solution to further enhance the performance of the processor.
In this work, implementation of a Memory Management System for a Stochastic ARM1136JF-S is elaborated in details. This Memory Management System includes a Memory Management Unit (MMU), a Level-one Cache Controller (L1 Cache Controller) with an Outstanding Critical Word First Buffering (OCWFB) mechanism, a System Coprocessor, and a Stochastic Coprocessor. A proposed OCWFB mechanism is implemented in the L1 Cache Controller to hide the CPU stalls caused by the L1 Cache Miss. In terms of CPU stalls, the performance reaches approximately 40% improvement. The Stochastic Coprocessor is a proposed coprocessor with a timing detection and a recovery mechanism inside. This coprocessor consists of two circuits: a cycle-based timing-detection circuit capable of detecting the environmental variations to enhance the error-resilience ability of Razor and a path-tracing timing-checking circuit capable of tracing the circuit path of L1 Cache and MMU to ensure no timing errors.
Subjects
隨機處理器
ARM1136JF-S記憶體管理單元
ARM1136JF-S第一階層高速緩存
ARM1136JF-S協同處理器
關鍵字優先
Type
thesis
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