Design considerations for FET-gated power transistors
Journal
IEEE Transactions on Electron Devices System
Journal Volume
ED-31
Journal Issue
12
Pages
1834-1837
Date Issued
1984-12
Author(s)
Abstract
This paper deals with a recently proposed FET-bipolar combinational power transistor configuration. The feasibility of this configuration has been demonstrated using discrete devices. Design considerations are given to hybridize this configuration. Copyright © 1984 by The Institute of Electrical and Electronics Engineers, Inc.
SDGs
Type
journal article