Power-Efficient FIR Filter Architecture Design for Wireless Embedded System
Resource
IEEE Transactions on Circuits and Systems II: Express Briefs 51 (1): 21-25
Journal
IEEE Transactions on Circuits and Systems II: Express Briefs
Journal Volume
51
Journal Issue
1
Pages
21-25
Date Issued
2004
Date
2004
Author(s)
Abstract
This paper presents a novel approach for implementing power-efficient finite-impulse response (FIR) filters that requires less power consumption than traditional FIR filter implementation in wireless embedded systems. The proposed schemes can be adopted in the direct form FIR filter and achieve a large amount of reduction in the power consumption. By using a combination of proposed methods, balanced-modular techniques with retiming and separated processing data-flow scheme with modified canonical signed digit (CSD) representation, experimental results show that the proposed scheme reduce 76% power consumption of the original direct-form structure with slight area overhead. © 2004, The Institute of Electrical and Electronics Engineers, Inc. All rights reserved.
SDGs
Type
editorial
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