Fast Algorithm and Architecture Design of Low-Power Integer Motion Estimation for H.264/AVC
Journal
IEEE Transactions on Circuits and Systems for Video Technology
Journal Volume
17
Journal Issue
5
Pages
568-576
Date Issued
2007
Author(s)
Abstract
In an H.264/AVC video encoder, integer motion estimation (IME) requires 74.29% computational complexity and 77.49% memory access and becomes the most critical component for low-power applications. According to our analysis, an optimal low-power IME engine should be a parallel hardware architecture supporting fast algorithms and efficient data reuse (DR). In this paper, a hardware-oriented fast algorithm is proposed with the intra-/inter-candidate DR considerations. In addition, based on the systolic array and 2-D adder tree architecture, a ladder-shaped search window data arrangement and an advanced searching flow are proposed to efficiently support inter-candidate DR and reduce latency cycles. According to the implementation results, 97% computational complexity is saved by the proposed fast algorithm. In addition, 77.6% memory bandwidth is further saved with the proposed DR techniques at architecture level. In the ultra-low-power mode, the power consumption is 2.13 mW for real-time encoding CIF 30-fps videos at 13.5-MHz operating frequency. © 2007 IEEE.
Subjects
ISO/IEC 14496-10 AVC; ITU-T Rec. H.264; Motion estimation (ME); VLSI architecture
Other Subjects
Integer motion estimation (IME); ISO/IEC 14496-10 AVC; ITU-T Rec. H.264; Video encoder; Algorithms; Bandwidth; Computational complexity; Computer hardware; Image coding; Trees (mathematics); VLSI circuits; Motion estimation
Type
journal article
File(s)![Thumbnail Image]()
Loading...
Name
61.pdf
Size
1.21 MB
Format
Adobe PDF
Checksum
(MD5):21dc296c6d317d7169e8e86435ca66cb