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College of Electrical Engineering and Computer Science / 電機資訊學院
Electrical Engineering / 電機工程學系
Formal Deadlock Checking on High-Level SystemC Designs
Details
Formal Deadlock Checking on High-Level SystemC Designs
Journal
IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
Pages
794-799
Date Issued
2010-11
Author(s)
Chun-Nan Chou
Chang-Hong Hsu
Yueh-Tung Chao
CHUNG-YANG HUANG
DOI
10.1109/ICCAD.2010.5653880
URI
http://scholars.lib.ntu.edu.tw/handle/123456789/359373
Type
conference paper