A 94GHz duobinary keying wireless transceiver in 65nm CMOS
Journal
IEEE Symposium on VLSI Circuits, Digest of Technical Papers
Date Issued
2014
Author(s)
Abstract
This work introduces a 94GHz duobinary keying wireless transceiver for point-to-point communications. It presents bandwidth efficiency twice as much as an OOK system and requires no carrier recovery and baseband circuitry to reduce power consumption. Designed and fabricated in 65nm CMOS, the transceiver achieves a 2.0-Gb/s data link with BER < 10-9 while consuming a total power of 265mW. © 2014 IEEE.
SDGs
Type
conference paper