A 511- $\mu$ W 89-dB-SNDR Asynchronous SAR-ISDM ADC With Noise Shaping Dynamic Amplifier and Time-Domain Noise-Slicing Technique
Journal
IEEE Journal of Solid-State Circuits
Date Issued
2023-01-01
Author(s)
Abstract
This work proposes a hybrid two-stage analog-to-digital converter (ADC) consisting of a coarse 3.3-V successive-approximation register (SAR) ADC and a fine 1.8-V comparator-based (CB) incremental $\Delta \Sigma$ modulator (ISDM) ADC. The coarse ADC boosts the maximum input amplitude to improve signal-to-noise and distortion ratio (SNDR), and the fine ISDM ADC adopts an asynchronous operation and a time-domain noise-slicing (TDNS) technique to improve power efficiency and conversion speed. Using the unequal data weighting of ISDM and the noise–slope relationship of the CB amplifier, the TDNS technique reconstructs the noise and power weighting of each cycle to optimize the figure of merit (FoM). Furthermore, the noise of the CB amplifier is suppressed by the noise-shaping (NS) technique. The ADC operates at a 370-kHz frequency and achieves 94.5/89.3-dB dynamic range (DR)/SNDR in a 185-kHz bandwidth (BW). It achieves a Schreier FoM of 174.88 dB and consumes 511 $\mu$ W.
Subjects
Asynchronous operation | Charge transfer | Clocks | comparator-based (CB) op | Current transformers | incremental <inline-formula xmlns:ali="http://www.niso.org/schemas/ali/1.0/" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> <tex-math notation="LaTeX">$\Delta\Sigma$</tex-math> </inline-formula> modulator (ISDM) | Noise shaping | noise-shaping (NS) | Power demand | time-domain noise-slicing (TDNS) | Transconductance | Voltage
SDGs
Type
journal article