A High Speed and Low Power Pipelined ADC for Powerline Communication System
Date Issued
2012
Date
2012
Author(s)
Lin, Ching-Fong
Abstract
Pipelined analog-to-digital converters (ADCs) have been widely utilized in high speed communication system for mid-high-resolution and high-speed sampling rate. In this thesis, we have implemented two high speed and low power 10-bit pipelined ADCs with sampling clock 100MS/s and 200MS/s respectively. The 200MS/s ADC is used as an analog front-end transceiver of HomePlug AV 2 power line communication system, which is combined with programmable gain amplifier as the receiver of whole system.
Implemented in TSMC 90nm technology, both chips applied 1.5-bit architecture to achieve high speed application and op-amp sharing technique to reduce the amount of op-amps being used to reduce power dissipation. Moreover, we use dynamic-range-doubling (DRD) technique to enlarge the dynamic range in pipelined ADC. The DRD technique not only increases the effective input range, but also decreases the gain and bandwidth requirement of op-amps. In post-layout simulation results of these two designs, FoM is 130fJ/step increased to 110fJ/step when the sampling frequency is raised from 100MS/s to 200MS/s, respectively. According to the measuring results, with 5MHz input frequency, the SNDR and SFDR achieve 42.5 dB and 47.5 dB at 50MS/s. The SNDR and SFDR are reduced to 31.9 dB and 45 dB at 100MS/s with 10MHz input frequency. The power consumption is 11mW at 100MS/s conversion rate.
Subjects
high speed
low power
pipelined ADC
ADC
Type
thesis
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