Atomic Scale Modeling and Simulation of the Gate Dielectrics (3/3)
Date Issued
2005-07-31
Date
2005-07-31
Author(s)
楊照彥
DOI
932212E002006
Abstract
The rapid scaling of Si-based CMOS devices has led
to silicon dioxide gate insulating film less than 2.0-nm
thick. By year 2008, the 70-nm generation needs
alternative gate dielectric material with higher K value
than that of silicon dioxide. Traditional TCAD tool is not
sufficient and atomic scale modeling and simulation is
needed for the IC design and analysis. In first year (I),
we have carried out the molecular dynamics simulation
using empirical interatomic potential and tight binding
theory to study the thin-film deposition. PC cluster tool
is established for parallel implementation. The results
indicate that the computational environment and
simulation model and code have been completed and
provide the basis for next stage quantum modeling/DFT
simulation.
Publisher
臺北市：國立臺灣大學應用力學研究所
Type
report
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