Network Accelerator Engine
Date Issued
2009
Date
2009
Author(s)
Yu, Shane-Feng
Abstract
Network Accelerator Enginebstracthe wired speed of the local area network has been increased from 10/100 Mbps to 1G/10bps recently and deep packet inspections are required in real-time by firewall machines to securehe Internet services. The processing of network packets has become the system’s major bottleneck.etwork accelerator engines can offload the computing need of CPU with a specific designircuit. In this thesis, we design and implement a Network Accelerator Engine to accelerate therocessing speed of TCP/IP protocol stack in an embedded system. The proposed offload engine isonsisted of four modules, namely, Datagram Receiver Module, Network Accelerator Module,Checksum Module, and Access Control List Module. In the proposed offload engine, we directly retrieve packets from the media access controller (MAC) and parse them for IP headers and payloadithout using any processor bus and interrupt. In a result, the packet processing speed does not depend on any software or CPU architecture.In current implementation in an Altera Cyclone II platform, we can achieve the data throughput of 100Mbps, which is the wired speed of the system’s MAC.
Subjects
Network Accelerator Engine
Type
thesis
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