Signal Integrity Analysis and Compensation Design of High Speed Memory Module
Date Issued
2009
Date
2009
Author(s)
Wang, Yu-Ning
Abstract
Memory module has become a essential product in modern computer systems. People are always pursuing digital products with faster operating frequency and tiny volume. For achieving this goals, there are many things that should be considered carefully in computer design, for example, the chip connector in memory modules and the electro- magnetic problems in power systems.here are two parts in this thesis. In the first part, the equivalent models of all discontinuities along the single-ended transmission path is extracted and then linked together for different function blocks of memory module, i.e. command/address line and data line. By this divided model, the influence of each discontinuity on signal integrity can be evaluated. Also, the accuracy of each model is verified through experiments. By means of the construction of the co-simulation environment considering signal and power integrity, and also active circuit models, the ground noise issue can be discussed as well. Similarly, this method can be applied to help extract equivalent models of differential clock line. The influence of signal integrity of differential clock line on the variation of sampling time can then be analyzed.n the second part, it is all about the compensation design for the imperfect effects on PCB and package structure. There are three kinds of imperfect effects on PCB that need to be overcome. The first one is the overall inductive behavior of signal vias, which mainly comes from the induction of ground bounce noise. It can be compensated by increasing the capacitive loading of signal vias. For the second one, unbalanced transmission lines can be used to mitigate the influence of signal vias with unmatched lengths connecting the chip inputs. For the third one, a design curve is established to provide the required dimensions of transmission line for impedance matching design of differential fly-by layout. As for the package layout, smaller effective inductance and less crosstalk effect can be achieved through the reassignment of power/ground pins among all signal pins.ith the above signal analysis methodology and compensation designs for high- speed memory module, it can help the engineers shorten the design process and make applications for memory module more efficiently.
Subjects
signal integrity
memory
compensation design
package
PCB
Type
thesis
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