Architecture Design of Convolutional Neural Networks for Face Detection on an FPGA Platform
Journal
IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
Journal Volume
2018-October
Pages
88-93
Date Issued
2018
Author(s)
Abstract
Convolutional neural networks (CNNs) have emerged to provide powerful discriminative capability, especially in the field of image recognition and object detection. However, their massive computation requirements, storage and memory accesses make them hard to be deployed on mobile or embedded systems. In this paper, a few optimizations for a CNN cascade face detection algorithm are proposed to increase throughput while minimizing computation, storage and bandwidth requirement under power constraints. First, the first net of the CNN cascade is converted to a fully convolutional network to reduce 83% of the computation. Second, network retraining is applied to quantize the model parameters from 32-bit floating-point to 2-bit fixed-point, resulting in 93.75% less parameter memory size. Finally, a CNN accelerator is implemented on a Xilinx ZYNQ FPGA board. © 2018 IEEE.
SDGs
Other Subjects
Convolution; Digital arithmetic; Embedded systems; Field programmable gate arrays (FPGA); Integrated circuit design; Neural networks; Object detection; Silicon compounds; Architecture designs; Bandwidth requirement; Convolutional networks; Convolutional neural network; Face detection algorithm; Model parameters; Power constraints; quantization; Face recognition
Type
conference paper