Deep Depletion Phenomenon in The C-V Characteristics of MOS Structure

In this thesis, deep depletion phenomenon in the C-V characteristics of MOS structure was investigated. In the beginning, a model was proposed to explain the deep depletion phenomenon in conventional inversion stage of C-V characteristics. Because the non-uniform characteristics results from the fringing field, devices are divided into the edge and bulk portions. And the enlarged C-V characteristic in the inversion stage is divided into three regions further, i.e., depletion-inversion region (Region 1), edge deep depletion region (Region 2), and bulk deep depletion (Region 3). In region 1, there are no deep depletion in both edge and bulk portions, so the capacitance keeps constant. As the gate bias voltage increases, the edge portion reaches its critical field which leads to the deep depletion and therefore the capacitance starts to drop in region 2. Increasing gate bias voltage further, the bulk portion reaches its critical field in region 3. In this region, the change of capacitance is mainly caused by the deep depletion in the bulk portion.
Then, the model was used to explain the effects of oxide thickness on deep depletion behavior and device area on deep depletion behavior. For the device with thicker oxide but with the same pattern size, it has the smaller uniform area ratio (K) in region 3, smaller change of capacitance in region 2 with respect to region 1, and larger initiation voltage of deep depletion. For the device with larger pattern size but with the same oxide thickness, it has larger uniform area ratio in region 3 and larger change of capacitance density in region 2 with respect to region 1.