Design of a Fast Fourier Transform Processor for DVB-Handheld System
Date Issued
2007
Date
2007
Author(s)
CHO, YU-JU
DOI
en-US
Abstract
Fast Fourier transform (FFT) is widely adopted as the demodulation kernel in the OFDM systems such as Digital Video Broadcasting – transmission system for Handheld terminals (DVB-H) system, etc. In the DVB-H system, a low power and variable-length FFT processor is required.
In this thesis, we firstly propose an FFT processor that reduces the power consumption by exploiting the ping-pong cached-memory architecture to decrease the access to main memory, and timely turning off the unused memory partitions to save energy in different sizes of the FFT.
Second, we design the triple-mode address generator to handle the address mapping of all storages in the three-size of FFT computations, and it includes the interleaving method to avoid data conflicts.
Then we propose two cost-efficient twiddle-factor coefficient design methods, “Sharing” and “Interpolation-then-Sharing”, to reduce the area of coefficient storages within the allowable loss of Signal-to-Quantized-Noise Ratio (SQNR). By using these methods, the area occupied by coefficient storage can be reduced by 67%. In 8192-point FFT, these modifications only cause 0.6dB loss of SQNR.
In the end of this thesis, we implement our proposed FFT processor for DVB-H system with TSMC 0.18μm 1P6M CMOS technology. The core size is 1.886×1.886mm2. The minimum latency to operate 8192-point FFT is 805μs with 86MHz clock rate. And the power consumption is 75.51mW. For DVB-H system, it processes the 8192, 4096, and 2048-point FFT with clock rates of 79MHz, 75MHz, and 71MHz, and consumes of 67.01mW, 53.16mW, and 39.45mW, respectively.
Subjects
快速傅利葉轉換
手持式數位視訊廣播
旋轉因子
FFT
DVB-H
Twiddle factor
Type
thesis
File(s)![Thumbnail Image]()
Loading...
Name
ntu-96-R92943104-1.pdf
Size
23.31 KB
Format
Adobe PDF
Checksum
(MD5):05e087db6f1d79470c25580337c448cb