Semi-Parallel Layered Decoder Architecture Design for Hierarchical QC LDPC Codes

The decoding algorithm of Low-Density Parity-Check (LDPC) codes is an iterative procedure. Therefore if the number of iterations can be reduced, the decoding throughput can be increased proportionally. The layered decoding algorithm is a fast converging decoding schedule which can reduce the number of iterations in half and has better coding gain performance than the conventional decoding schedule, two phase schedule. In this thesis, a LDPC decoder architecture using a fast converging layered decoding algorithm is presented. This hierarchical architecture is highly scalable and configurable. Two-level
hierarchical quasi-cyclic LDPC codes are used to provide good coding gain and low error floor at long codeword length. We also develop a novel compensation method, mixedmode min sum algorithm, which can provide better BER performance and need less iterations than the scaling min sum. Several designs are implemented on Altera Stratix II EP2S130 FPGA. The LDPC decoder implementation with 2 first level decoding blocks and 32 second level decoding units can achieve close to 1 Gbps information throughput.