A 12-bit 210-MS/s 5.3-mW pipelined-SAR ADC with a passive residue transfer technique
Journal
IEEE Symposium on VLSI Circuits
Date Issued
2014-06
Author(s)
C-Y Lin
Abstract
A 210 MS/s dual-channel 12-bit analog-to-digital converter (ADC) employing a pipelined successive approximation (SAR) architecture is presented. The ADC is partitioned into 3 stages with passive residue transferring between the 1 st and the 2 nd stages and active residue amplification between the 2 nd and the 3 rd stages. The ADC consumes 5.3 mW from a 1-V supply and achieves an SNDR of 63.48 dB at a 5-MHz input and 60.1 dB near Nyquist-rate.
SDGs
Type
conference paper