A Fully Digital External Calibration Technique for 1-bit/stage Pipelined ADC
Date Issued
2007
Date
2007
Author(s)
Yu, Yuan-Chi
DOI
en-US
Abstract
In this thesis, a fully digital calibration scheme for the 1-bit/stage pipelined ADC is presented. It is extended from the existing digital calibration algorithm that still suffers arbitrary large DNL in some output codes. The proposed technique extracts these codes from the histogram data and then applies proper modification to them to enhance the linearity. Except for the input ramp signal, the whole calibration is performed in the digital domain and is done at the nominal ADC speed. The approach does not require any modification to the original analog section of the ADC and is convenient to be extended to the different structures of the pipeline stage. The analysis exhibits a bound of 1/3 LSB in the DNL. Simulation result also shows at least 1-bit improvement in the INL. The digital hardware implementation scheme is presented as well.
Subjects
管線式 類比數位轉換器 校正
pipeline ADC Calibration
Type
thesis
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