An OPLL-Based Spread Spectrum Clock Generator for SATA III
Date Issued
2010
Date
2010
Author(s)
Chiang, Chun-Yu
Abstract
As portable devices are widely used nowadays, the high-speed interfaces between the personal computer and the external storage devices are becoming critical in order to achieve high data transmission rate. When operating at high data rate, the systems often suffer from the electromagnetic interference (EMI) which is caused by the high-frequency clock. This non-ideal effect in electronic products is a serious issue which must be dealt with. Serial AT Attachment (SATA) is one of the most promising technologies providing large bandwidth up to 6 Gb/s. SATA specification defines an EMI reduction method using spread-spectrum clocking (SSC) to reduce the peak EMI emission by spreading the carrier frequency.
A spread spectrum clock generator (SSCG) based on an offset phase-locked loop (OPLL) for the Serial AT Attachment 3 (SATA III) is presented in this thesis. In the proposed architecture, a low-frequency spread spectrum signal is synthesized by a direct digital frequency synthesizer (DDFS) and mixed with a high frequency signal to produce a higher modulated reference source. The OPLL is employed to lock its output with the modulated reference to generate the desired spread spectrum clock. This SSCG is fabricated in a 0.11-μm CMOS technology and its area is 1.071 x 0.945 mm2. It draws 15.22 mW from a 1 V supply.
Subjects
OPLL
SATA
SSCG
Type
thesis
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