An All Digital PLL for Spread Spectrum Clock Generator
Date Issued
2011
Date
2011
Author(s)
Su, Cheng-Dow
Abstract
Recent advances in integrated circuit (IC) technology make fabrication processes very suitable for digital design. In order to satisfy the market requirement, small area and low voltage designs are mandated nowadays. It is easy to redesign with process changes for digital designs.
The all-digital phase-locked loop (ADPLL), one of the most recent and significant advancements in the integrated circuits, offers the remarkable advantage of replacing the charge pump and the loop filter with digital loop filter.
The spread spectrum clock generator (SSCG) can be applied to many systems due to its characteristic of spreading the energy of frequency harmonics and reducing the radiated power per unit bandwidth.
In this thesis, an all-digital phase-locked loop application for SSCG is implemented in this paper. We use two-stage delta-sigma modulator to improve the resolution of DSM in spread-spectrum clock function. Finally, the experimental ship is fabricated in a TSMC 90nm CMOS process.
Subjects
All-digital phase-locked loop (ADPLL)
spread spectrum clock generator (SSCG)
Type
thesis
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