A hardware efficient 64-QAM low-IF transceiver baseband for broadband communications
Resource
Advanced System Integrated Circuits 2004. Proceedings of 2004 IEEE Asia-Pacific Conference on
Journal
Advanced System Integrated Circuits 2004
Pages
Proceeding-s
Date Issued
2004-08
Date
2004-08
Author(s)
Chang, Ching-Chi
Shiue, Muh-Tian
Wang, Chorng-Kuang
DOI
N/A
Abstract
This paper presents a hardware efficient VLSI design of digital baseband for 64-QAM communication systems over the last-mile cable network. This VLSI system design involves a cost-efficient architecture of the adaptive equalizer and a two-phase linear architecture of the pulse shaping filters, which reduce the hardware requirement by a factor of four comparing with traditional quadrature direct form FIR filters. In this design, the two-fold carrier recovery loop possesses a pull-in range of /spl plusmn/100kHz (i.e. /spl plusmn/18, 500ppm of the symbol rate) and -82dBc jitter suppression. Based on the proposed multi-staged LMS-based fractionally-spaced equalizer, the receiver realizes the symbol spaced timing recovery in a /spl plusmn/200ppm tolerance of the symbol rate. The acquisition time of the proposed 64-QAM blind adaptive system is 7ms, and the transceiver reaches the operation speed of the case for 32.28Mb/s 64-QAM low-IF digital CATV system over NTSC 6MHz bandwidth channels. Using 0.35 /spl mu/m CMOS technology, the transceiver design occupies a chip area 5.5mm /spl times/ 5.5mm and power consumption 1.35W (1.0W for RX) when the power supply is 3.3V.
SDGs
Type
journal article
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