A Multi-Level Runtime Reconfigurable Array (RTRA) for Multi-Program ML and DSP Acceleration in 16-nm CMOS
Journal
2025 IEEE Asian Solid-State Circuits Conference, A-SSCC 2025 - Proceedings
Start Page
25
End Page
27
Date Issued
2026-01-28
Author(s)
Lee, Hongseok
Ling, Tim
Burd, Jack
Yang, Yao-Kai
Chang, Nian-Shyang
Chen, Wen-Ching
Chen, Chi-Shi
Lee, Michael Kuan-Tse
Marković, Dejan
Abstract
Emerging applications with dynamic DSP and ML workloads demand high-performance, energy efficient, and low-latency hardware reconfiguration. However, existing reconfigurable architectures [1-2] and scheduling solutions [3-4] rely on slow off-chip software scheduling and mapping that is based on inherently slow and non scalable 2D polygon placement algorithms. In addition to moving the scheduler on-chip, hardware array needs repartitioning to achieve fundamentally superior scheduling and mapping
Event(s)
2025 IEEE Asian Solid-State Circuits Conference, A-SSCC 2025
Publisher
IEEE
Type
conference paper