A 50.8-53-GHz clock generator using a harmonic-locked PD in 0.13-μm CMOS
Journal
IEEE Transactions on Circuits and Systems II: Express Briefs
Journal Volume
55
Journal Issue
5
Pages
404-408
Date Issued
2008-05
Author(s)
Abstract
A 50.8-53-GHz clock generator with a quadruplicate-harmonic-locked phase detector (PD) is presented to achieve a low spur and a low reference frequency. The proposed quadruplicate-harmonic-locked PD, a low-voltage Colpitts voltage-controlled oscillator, and a wide-range divide-by-2 divider are also presented. This clock generator has been fabricated in a 0.13-μm process. The measured reference spur is - 59.88 dBc at 51.02 GHz with an input reference frequency of 199.3 MHz. The area is 0.93 mm × 1 mm with the on-chip loop filter and pads. It dissipates 87 mW without buffers from a 1.5-V supply. © 2008 IEEE.
Subjects
Clock generator; Phase detector; Rference spur; Voltage-controlled oscillator (VCO)
SDGs
Other Subjects
Circuit oscillations; Clocks; Harmonic generation; Variable frequency oscillators; Clock generator; On-chip loop filter; Quadruplicate-harmonic-locked phase detector (PD); Voltage-controlled oscillator; CMOS integrated circuits
Type
journal article