Placement Optimization of Flexible TFT Digital Circuits
Date Issued
2010
Date
2010
Author(s)
Liu, Wei-Hsiao
Abstract
Flexible TFT technology has many advantages over conventional silicon technology such as low cost and short manufacturing time. As the technology advances, flexible TFT technology now has the ability to implement large-scale digital circuits. Currently the most important problem of flexible TFT technology is the change in mobility when the TFT is bent, and thus the circuit timing is changed when the chip is bent. A placement optimization of flexible TFT digital circuits is proposed to reduce the percentage of clock frequency that has to be slowed down in order to avoid setup time violations. Three optimization modes are supported by the proposed technique for the designer to choose based on different package and bending assumption. A standard cell library is characterized using an OTFT model provided by industrial technology research institute in this thesis. Our experimental results show that the percentage of clock frequency that has to be slowed down is reduced by half when the whole chip is flexible and below 4% when part of the chip is fixed to a rigid package. To the author’s knowledge, this is the first placement optimization tool for flexible TFT digital circuits.
Subjects
Placement Optimization
Flexible TFT Technology
Digital Circuits
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