Efficient Encoding for Dual-Diagonal Structured LDPC Codes Based on Parity Bit Prediction and Correction
Resource
Circuits and Systems, 2008. APCCAS 2008. IEEE Asia Pacific Conference on, 1648-1651
Journal
APCCAS 2008-2008 IEEE Asia Pacific Conference on Circuits and Systems
Pages
1648-1651
Date Issued
2008
Date
2008
Author(s)
Lin, Chia-Yu
Wei, Chih-Chun
Ku, Mong-Kai
Abstract
In this paper, an efficient encoding scheme for dual-diagonal structured LDPC codes is proposed. Our encoding algorithm employs parity bit prediction and correction to break up the data dependency within the encoding process. The encoder can achieve higher level of parallelism and better hardware utilization. The number of required clock cycles for encoding one codeword can be reduced to achieve higher throughput performance. The proposed scheme can be directly applied to IEEE 802.11n and 802.16e dual-diagonal codes without any matrix modification. A low-complexity encoder architecture is proposed and implemented to verify these characteristics. Results show that the proposed architecture outperforms conventional works in terms of throughput and throughput/area ratio.
Type
conference paper
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