Hierarchical Analog Circuit Placement
Date Issued
2009
Date
2009
Author(s)
Lin, Po-Hung
Abstract
In modern analog layout design, it is very important to consider layout design hierarchy for better layout quality and circuit performance especially when conducting analog device placement. To reduce unwanted parasitic effects arising from device mismatches and circuit sensitivities due to thermal gradients and process variation, it is also essential to consider device matching, device symmetry, and device proximity in each hierarchy. In addition, when integrating power and non-power devices on the same chip, the preferred thermal profile should be further considered for better thermal device matching.n this dissertation, we present a hierarchical analog placement approach with the consideration of layout design hierarchy by introducing the novel hierarchical B*-tree (HB*-tree) and automatically symmetric-feasible B*-tree (ASF-B*-tree) floorplan representations. To further achieve the most important layout constraints including, device matching, (hierarchical) device symmetry, and (hierarchical) device proximity, as well as the preferred thermal profile, we propose: (1) a pattern-based matching placement and routing approach to facilitate the layout generation of matching device groups, such as currentirrors, (2) the first linear-time packing algorithm for analog placement with symmetry constraints by introducing the symmetry-island formulation for symmetry device groups, such as differential circuits, (3) the first analog placement approach based on hierarchical circuit clustering by exploring the correlation between the proximity constraints and properties of HB*-trees, and (4) the first thermal-driven analog placement considering thermal deviceatching by directly optimizing the thermal profile on the chip.xperimental results based on the analog benchmark circuits show that our hierarchical analog placement approach is the most effective one to handle analog placement with matching, (hierarchical) symmetry, and (hierarchical)roximity constraints. It can achieve the best published runtime efficiency and analog circuit performance/accuracy with the least impact due to the thermal gradient.
Subjects
Physical Design
Floorplanning
Placement
Analog Circuit
Type
thesis
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