A 3x-Oversampling Hybrid Clock and Data Recovery Circuit with Programmable Bandwidth
Date Issued
2012
Date
2012
Author(s)
Jheng, Jia-An
Abstract
In recent years, applications of wirelan communication have been growing rapidly. Meanwhile, high-speed I/O is used to increase the bandwidth between chips in a computer or network. The clock and data recovery (CDR) circuit is responsible for reconstructing the original transmitter bit-stream at the receiver. The CDR has been viewed as a feedback control system that adjusts its output clock according to the phase movement of the input data in the conventional phase-tracking architecture. However, there is another structure of CDR, blind-oversampling based CDR. This CDR is a feed-forward architecture and thus has no phase-tracking between clock and input data. These two types of CDR have their advantages and disadvantages in jitter tolerance performance with different jitter frequency regions. Based on the point at this issue, we combine these two types of CDR and use the programmable bandwidth to enhance the performance jitter tolerance. So the jitter tolerance will be boosted especially in the jitter frequency regions which are below the loop bandwidth.
In our thesis, the 3x-oversampling hybrid clock and data recovery circuit with programmable bandwidth is proposed. The measured peak-to-peak jitter of recovered clock is 99.15mU (88.13ps) and the measured jitter tolerance results are 1.2UI@10MHz, 5.5UI@1MHz, and 35UI@100kHz with 4.5Gb/s data rate and PRBS length = 10, respectively. The power consumption is 46.2mW with 1.1V supply voltage. The total area of chip is 0.98mm2 and this chip is fabricated in the UMC 55nm CMOS technology.
Subjects
Clock and data recovery
Hybrid CDR
Oversampling CDR
Jitter tolerance
Type
thesis
File(s)![Thumbnail Image]()
Loading...
Name
ntu-101-R97943021-1.pdf
Size
23.32 KB
Format
Adobe PDF
Checksum
(MD5):f9282637e4cd9935b2732d2b7372108b