A Variable-Interval Oversampling Clock and Data Recovery Circuit Using Interpolation
Date Issued
2009
Date
2009
Author(s)
Chiang, Yu-Hsing
Abstract
A clock and data recovery circuit (CDR), which is a part of a receiver, plays an important role in a communication system. Since bandwidth of transmission channels is limited, severe jitter is produced. A CDR with higher jitter tolerance provides higher-accuracy data, but large magnitude of jitter and asymmetry of jitter reduce jitter tolerance. Using oversampling clocks for CDR alleviates the problem mentioned above, resulting in enhanced jitter tolerance and lower BER. fractioned-rate oversampling CDR is applied in consideration of speed and jitter tolerance. A quarter-rate 3x-oversampling CDR was proposed, where the Intervals between the edge-sampling clocks and decision clocks are variable according to incoming data eye diagram. As a result, the CDR’s jitter tolerance is better than a fixed-interval CDR’s one. The thesis proposed a modified method of clock generation whose advantages are relieving the restriction of the number stage of delay cells, a limitation of the maximum magnitude and the restriction of types of delay cells. The CDR is designed in 0.18-μm CMOS technology and targeted to fit the specification of fibre channel. The simulated peak-to-peak data jitter is 22-ps at data rate of 5-Gbps, the measured peak-to-peak and RMS jitter are 76.67-ps and 9.07-ps, respectively, at data of 4.25-Gbps. The chip size is 0.74*0.84-mm2, and the measured power consumption is about 170-mW including output buffers.
Subjects
Variable Interval
Oversampling
Clock and Data Recovery
Interpolation
Type
thesis
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