Design and Application of Analog-to-Digital Converters and Digital-to-Analog Converters
Date Issued
2010
Date
2010
Author(s)
Chang, Yu-Lun
Abstract
In Chapter 3, a 6-bit, 1MHz, low power DAC is presented. This chip is designed to be an arbitrary waveform generator for the neural stimulator.
In Chapter 4, a 10-bit, 1MHz, low power DAC using the proposed “C-R hybrid architecture” is presented. With this architecture, the DAC can achieve high resolution while using lower power and smaller area comparing with other architecture.
In Chapter 5, a 10-bit, 50MHz, pipelined ADC is presented. By using the “opamp current reuse technique”, the analog power consumption is reduced by half comparing with the conventional pipelined ADC.
All chips in this thesis are designed and fabricated using TSMC 2P4M 0.35μm CMOS technology.
Subjects
DAC
ADC
Switched-Capacitor
Hybrid
Pipelined
Type
thesis
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