CMOS 2.4-GHz receiver front end with area-efficient inductors and digitally calibrated 90-degree delay network
Journal
IEEE ISCAS 2002
Pages
77
Date Issued
2002-05
Author(s)
Chih-Chun Tang
Abstract
A 2.4-GHz CMOS Hartley image-reject receiver utilizes the miniature 3D inductor and the digitally calibrated 90/spl deg/ delay network is proposed. Compared with the conventional planar inductor, the proposed miniature 3D inductor saves 80% silicon area without degrading the quality factor. In addition, employing the digitally calibrated 90/spl deg/ delay network rather than the RC-CR network, which is used in the traditional Hartley: receiver, can tune the delay dynamically such that it is insensitive to the temperature and process variations. A prototype chip with a fully integrated low-noise amplifier (LNA) followed by the proposed image-reject mixer was fabricated in a 0.35-/spl mu/m single-poly-four-metal (1P4M) CMOS technology and the active area is 3.13 mm/sup 2/. While operating in 2.4 GHz, this receiver achieves 30 dB image-rejection ratio (IRR), -3 dB third-order input inter-modulation intercept point (IIP3), and 11 dB noise figure (NF) with 54 mW power consumption from a 3.3-V supply.
SDGs
Type
conference paper