Technique for In-Band Phase Noise Reduction in Fractional-N Frequency Synthesizers
Journal
IEEE Asian Solid-State Circuit Conference
Pages
96:1-96:6
Date Issued
2016
Author(s)
Abstract
A fractional-N PLL employing a dual-frequency clock generator is proposed to achieve lowering the in-band phase noise. The architecture enables the PFD/CP to operate in the linear region to avoid noise-folding effect. An optimum operating condition can be tuned to achieve the best in-band phase noise. The proposed techniques are employed in a 800-MHz fractional-N PLL fabricated in a 0.18-μm CMOS process. The experimental results demonstrate that the integrated rms jitter (10 kHz to 10 MHz) in the fractional-N PLL can be greatly improved from 26.45 ps to 3.91 ps. This fully-integrated PLL dissipates 23.5 mA from a 1.8-V supply.
SDGs
Type
conference paper