A De-skew Clock Generator for Arbitrary Delay and An All-Digital Continuous Rate Wide-Capture Range CDR

This thesis contains two chips one is DLL the other is CDR implemented in standard CMOS technology.
The delay locked loop (DLL) is widely used for high-speed memory interface circuits and clock multipliers to perform clock de-skew. The DLL offers two attractive advantages over conventional PLL: one is a faster locked time, and the other is unconditionally stability. First, half of this thesis proposed a 300- to 800-MHz low jitter and ringing effect free de-skew clock generator for arbitrary delay. The generator is designed and fabricated in a 0.18-μm CMOS process. The power consumption is 10mW at 800MHz.
The rapid growth of data transmission demands low-cost communication systems operating at frequencies over several GHz. The pursuit for larger bandwidth converts the transmission medium from copper wire to fiber gradually. Clock and data recovery (CDR) circuits both remove the jitter in the data and retime the data for the succeeding circuits. A complete investigation and implementation of this CDR from a digital circuit point of view will be elaborated in this research.
The other half of this thesis proposed a TDC-based all-digital wide capture range CDR and is implemented by standard 90-nm CMOS technology. The proposed architecture can increase the capture range.