Design on a Deserializer and the PCS Service Interface Circuit for the 10GBASE-LX4 Ethernet Receiver
Date Issued
2004
Date
2004
Author(s)
Hsu, Wern-Jir
DOI
en-US
Abstract
With the fast proliferation and development of the Internet, the demand for high-speed communication network has grown progressively. The bandwidth of local area network (LAN) already enters the generation of the 10 Gigabit Ethernet recently. In the standard of IEEE 802.3ae, which is defined for the 10 Gigabit Ethernet, 10Gbase-LX4 specification utilizes low-cost laser diodes, optical diodes, and multi-mode or single-mode fibers. 10GBase-LX4 will play an important role in the Ethernet in the near future.
In this thesis, first we design a deserializer for 10GBase-LX4 receiver. The deserializer functions as a data type converter. As a high speed data stream came from Clock/Data Recovery is input, the deserializer not only achieves byte-level synchronization by detecting the alignment character, but it also converts the high-speed input stream into lower-speed parallel output.
Meanwhile, there are four independent lanes in a 10GBase-LX4 transceiver. Due to the imperfectness of each lane, the data skew between lanes will be observed at the receiver. Thus we design a physical coding sublayer (PCS) interface circuit that achieves multi-lane word alignment and provides the required data pattern to the following Media Access Control (MAC) layer for further processing.
Subjects
百億位元乙太網路接收機
一對十序列-並列轉換器
同步字元偵測器
相位選擇電路
實體編碼次層介面
通道時脈資料校正電路
1:10 Deserializer
Comma character detector
10GBase-LX4 Receiver
Phase selection circuit
Multi-lane alignment circuit
Physical coding sublayer (PCS) interface
Type
thesis