Design of all-digital phase-locked loop implemented in LTPS TFT process
Date Issued
2009
Date
2009
Author(s)
Kuo, Yen-Ting
Abstract
The thesis presents an all-digital phase-locked loop (ADPLL) as a clock generator implemented in 3um LTPS TFT process. The output frequency range of the ADPLL is from 0.625MHz to 12MHz, the multiplication factors of the reference clock are 1 to 30, and the time resolution of the coarse-tuning part of the DCO is 5.6 ns and that of the fine-tuning part is 0.25ns by simulation. The measuring result of the time resolution of course-tuning part is 8ns. PLL is an essential module in many applications, and the trend of development of PLL is toward all-digital realization. The nature of digital circuits has high immunity against process deviation and it is easy for circuits to be ported among different processes.
Subjects
LTPS TFT
all-digital phase-locked loop
Type
thesis
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ntu-98-R94943089-1.pdf
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