Quick RTL Synthesis for Design Analysis and Verification
Date Issued
2006
Date
2006
Author(s)
Huang, Chun-Fu
DOI
en-US
Abstract
In this thesis, we proposed a quick register transfer level(RTL) front end for design analysis and verification. Our front end consists of three parts: (1) an RTL parser that supports most of the synthesizable Verilog subset and various library formats; (2) an elaborating process that generates control data flow graph(CDFG) and can be used for design intent extraction and (3) a logic synthesizer that translates the design into a word-level netlist and writes out a structural Verilog file. We have been able to read in several designs from other design teams and have verified the correctness of our front end by the Cadence Conformal Logic Equivalence Checker(LEC). With the word-level data structure and high-level design intent extraction at hand, we will be able to conduct more research on the design debugging and verification in the future.
Subjects
邏輯合成
設計分析
logic synthesis
design analysis
Type
thesis
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