All-Digital Fast-Locking Delay-Locked Loop with Duty Cycle Correction
Date Issued
2006
Date
2006
Author(s)
Chen, Bo-Jiun
DOI
en-US
Abstract
With the evolution and continuing scaling of CMOS technologies, the demand of high speed and high integration density VLSI systems have the exponential growth recently. However, the synchronization problem among IC modules is undoubtedly important and becoming one of the bottlenecks for high performance systems. Phase-locked loops (PLLs) and delay-locked loops（DLLs）have been widely employed for the purpose of synchronization. Due to the difference of their configurations, the DLLs are preferred for their unconditional stability and faster locking time than the PLLs. Additionally, a DLL offers better jitter performance than a PLL because noise in the voltage-controlled delay line (VCDL) does not accumulate over many clock cycles. The all-digital design has high portability and scalability across different technology process. Its high integrity, low power, and low jitter performance can be easily incorporated into several systems. A clock with 50% duty-cycle is extremely important in many double-rate systems such as DDR-SDRAMs and analog-to-digital converters. Therefore duty-cycle corrector (DCC) is needed to correct duty cycle as 50%.
This thesis contains three design and realization of the all-digital DLL and DCC circuits. First of all, an all-digital 50% DCC is presented. The features of the proposed DCC include a wide operation frequency range, a wide input duty cycle range for the input clock, and a faster correction speed. The acceptable duty cycle and frequency range of the input clock is 25%-75% and 250MHz-600MHz, respectively. The correction time is 8ns at 500MHz. Besides, this DCC can save power consumption by turning off half of the delay cells.
Secondly, a fast-locking all-digital DLL with 50% duty cycle is proposed. Based on the proposed architecture, not only the phase alignment of input and output clocks can be achieved, but also the duty cycle of the output clock can be corrected to 50%. It can synchronize in four cycles. Besides, the proposed delay line plays not only delay cells but also a time-to-digital converter (TDC). So it reduces active area and power effectively. The input frequency range can operate within 300MHz-500MHz. The accepted input duty cycle range is 40%-60%.
Thirdly, a wide-range anti-reset all-digital DLL is presented. The total system does not need any outside-reset signal to reset the system when the input clock frequency changes a lot, due to the dynamic frequency detector. The proposed binary TDC can reduce effectively hardware compared with a traditional TDC. Besides, the while system is a closed loop and it can track PVT variations. The input frequency range can operate within 62.5MHz-625MHz. It spends four to six cycles to get synchronization.
Subjects
延遲鎖相迴路
全數位
時間到數位轉換器
工作週期校正器
delay locked loop
all-digital
time-to-digital converter
duty cycle corrector
Type
thesis
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