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College of Electrical Engineering and Computer Science / 電機資訊學院
Electrical Engineering / 電機工程學系
An Analysis of ATPG and SAT algorithms for Formal Verification
Details
An Analysis of ATPG and SAT algorithms for Formal Verification
Journal
International High Level Design Validation and Test Workshop
Pages
177-182
Date Issued
2001-11
Author(s)
G. Parthasarathy
K-T. Cheng
CHUNG-YANG HUANG
DOI
10.1109/HLDVT.2001.972826
URI
http://scholars.lib.ntu.edu.tw/handle/123456789/294475
SDGs
[SDGs]SDG16
Type
conference paper
