VLSI Compact and Accurate Gate Timing Modeling and Efficient Timing Simulation Algorithm

Static Timing Analysis (STA) is very important for nanometer integrated circuit design. The accuracy of STA still needs to be improved while minimizing runtime penalty. This thesis focuses on two important aspects of STA. First, an efficient and accurate method is needed for obtaining the behavior model of all standard cells. With the existing large number of standard cells, a substantial amount of simulation data has to be recorded to maintain the accuracy. This in turn results in an unbearable amount of memory overhead. We present a method to compress the large gate timing information, to minimize the amount of memory overhead. A compression ratio of 19X and a Space Saving of 95% can be achieved and the compacted data still maintained a very high level of accuracy. Second, the interconnect delay dominates the circuit path delay for today''s CMOS technology due to the effect of the high impedance interconnect. However, parasitic capacitance and inductance in interconnections have begun to increasingly affect the signal quality and the computed complexity. We present a new fast recursive convolution method for timing simulation. Experimental results show very accurate result of 1% error and one thousand times faster runtime when compared with SPICE.