SoC HW/SW Verification and Validation

In modern SoC design flow, verification and validation are key components to reduce time-to-market and enhance product quality. To avoid trade-offs between timing accuracy and simulation speed in RTL simulation and C++/SystemC virtual prototyping, FPGA prototyping has become a better choice in the design flow. However, the time-consuming bring-up procedure and insufficient debugging visibility has impaired its potential strengths in verification and validation. In this paper, we present the technology from InPA Systems in which four different modes of operations, RTL-FPGA co-simulation, SystemC-FPGA co-emulation, vector prototyping, and in-circuit prototyping, are supported. With these different modes of FPGA operations, users can develop and verify their SoCs in different stages of the design flow with different abstraction levels. This methodology efficiently and robustly completes the SoC HW/SW verification and validation flow. ©2011 IEEE.