Low-Power MCU With Embedded ReRAM Buffers as Sensor Hub for IoT Applications
Journal
IEEE Journal on Emerging and Selected Topics in Circuits and Systems
Date Issued
2016
Author(s)
Abstract
This paper proposes embedding 256 Kb resistive random-access memory (ReRAM) in a microcontroller unit as a data buffer for communicating with a stand-alone flash memory. In this study, the chip was manufactured using a combination of the TSMC 0.18 μm process and the Industrial Technology Research Institute ReRAM back-end-of-line process. The ReRAM was equipped with a novel sense amplifier that had three magnification times for the reference cell current for increasing the read yield by 32%. Furthermore, the ReRAM controller included built-in self-test, built-in self-repair, a shortened Bose-Chaudhuri-Hocquenghem (99, 64, 5) error-correlating code, and asymmetric coding can yield ReRAM up to approximately 100%. When compared with the conventional dynamic random-access memory (DRAM) buffer, the proposed architecture reduces the system execution time by 25% and the power consumption by 15% at 25 MHz. Simulations also showed that the ReRAM buffering runs at least 51% faster when compared with the use of other nonvolatile memories such as ferroelectric RAM, phase change RAM, and conduct-bridge RAM. Although ReRAM buffering is just competitive in speed and power consumption of spin-transfer torque magnetor resistive RAM buffering, ReRAM has clear advantages in area, cost, and reliability.
SDGs
Type
journal article