High Speed AC Coupled Interconnection Systems and PI/SI Effects on I/O Circuits with Decoupling Capacitors
Date Issued
2010
Date
2010
Author(s)
Ye, Ren-Bang
Abstract
In recent years, for enhancing the speed of chip-to-chip communication, some papers propose a signaling method which transmits data using AC coupled technique. It features low power consumption and high communication bandwidth, and the system is called AC coupled interconnection. We propose a pulse receiver which is fabricated with 0.18μm CMOS process. The circuit can operate at 10Gb/s and the power consumption is 40mW. Inductive peaking and reversed tripled-resonance network(RTRN) technique are adopted to enhance the bandwidth of the receiver.
In this thesis, we also propose an AC coupled receiver which is high speed, low power, but with small chip area with 90nm CMOS process. Active peaking technique is applied to improve the operation speed of the AC coupled receiver, which can work at 13.5Gb/s and only consume 5.5mW.
In addition, we discuss the impact of power integrity and signal integrity for interface circuits. A test chip with multiple transmitters operating at 3.2Gb/s and on-chip decoupling capacitors is implemented. By changing the number of inactive transmitters and capacitors, power integrity issue is discussed. Finally, we observe the eye diagrams of the transmitter in different conditions and assess the issue of signal integrity.
Subjects
interface circuit
AC-coupled
pulse signaling
reversed triple-resonance network
active peaking
power and signal integrity
decoupling capacitor
Type
thesis
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