A novel 0.7 V two-port 6T SRAM memory cell structure with single-bit-line simultaneous read-and-write access (SBLSRWA) capability using partially-depleted SOI CMOS dynamic-threshold technique
Resource
SOI Conference, 1999. Proceedings. 1999 IEEE International
Journal
SOI Conference, 1999. Proceedings. 1999 IEEE International
Pages
-
Date Issued
1999-10
Date
1999-10
Author(s)
Liu, S.C.
Kuo, J.B.
DOI
1078-621X
Abstract
Summary form only given. This paper reports a novel low-voltage two-port 6T SRAM memory cell structure with single-bit-line simultaneous read-and-write access capability using a partially-depleted SOI CMOS dynamic-threshold technique. With an innovative approach connecting the body terminal of an NMOS device in the latch and the write access pass transistor to the write word line, this 6T memory cell can be used to provide SBLSRWA capability for 0.7 V two-port SOI CMOS VLSI SRAM, as verified by MEDICI results.
SDGs
Type
journal article
File(s)![Thumbnail Image]()
Loading...
Name
00819860.pdf
Size
113.23 KB
Format
Adobe PDF
Checksum
(MD5):a501358777cc44ff6e3c9a324da7cf13