RTL-to-TL Model Generation Based on Protocol Abstraction Techniques
Date Issued
2014
Date
2014
Author(s)
Cheng, Chia-Hsun
Abstract
Simulation-based verification is a fundamental verification methodology for validating digital designs. The ever-increasing complexity of system arises from design growing from simple controllers to complex System-on-Chips (SoCs).
The complexity leads to the slow simulation-speed for system-level Register Transfer Level (RTL) simulation that cannot catch up with the growing complexity of integrated RTL blocks on a SOC. This work proposes the techniques to increase the simulation speed by transforming the designs from RTL to transaction-level (TL) models in SystemC, a standard for modeling electrical systems.
From RTL to TL, the timing granularity is different and the notion of equivalence should be redefined to cross different abstraction levels. To achieve the abstraction and maintain the equivalence, we defined the Protocol Specification Language (PSL) for user to formulate the handshaking signals and cared transaction boundaries in RTL. From the RTL description and PSL specification, the formal model – Extended Finite State Machine (EFSM) can be extracted and simplified based on formal and compiler transformation techniques. In the last code generation phase, we perform several optimizations and generate corresponding TL SystemC simulation models.
The experimental results show that the simulation speed can be increased several times and the manual effort to craft the correct untimed SystemC model can be alleviated.
Subjects
SystemC
事件轉移階層模型
虛擬模擬平台
協定規格語言
擴充式有限狀態機
二元決定圖
編譯器轉換技術
Type
thesis
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