A 300KHz bandwidth 3.9GHz 0.18μm CMOS fractional-N synthesizer with 13dB broadband phase noise reduction
Journal
European Solid-State Circuits Conference
Pages
451-454
Date Issued
2011
Author(s)
Abstract
This paper describes a sigma-delta fractional-N synthesizer architecture with fractional spur and quantization noise cancellation. Modified phase frequency detector (PFD) and charge pump are utilized to improve the linearity. A delay line with 54 ps delay resolution is inserted between the reference signal and PFD to compensate phase errors. At least 13 dB fractional spur and quantization noise improvement could be achieved with 300 KHz loop bandwidth at 3.9 GHz synthesized frequency in a standard 0.18 μm CMOS technology which occupies 1.21×1.23 mm 2 . The improvement can be further enhanced when delay resolution is improved with more advanced process.
SDGs
Type
conference paper