The FPGA implementation of a jitter measurement infrastructure IP
Date Issued
2004
Date
2004
Author(s)
Liu, Yuan-Shuang
DOI
en-US
Abstract
Jitter is an important subject of research for modern high-speed circuits and data transmission systems. With the increasing data rates of new high-speed I/O and bus standards, the measurement of jitter is rapidly becoming a necessity for ensuring error free digital communication. However, measuring high-speed clock jitters is a difficult task. It usually relies on expensive ATE (automatic test equipment) and usually requires long test time. Furthermore, the situation is getting worse as the trend of system integration onto a single chip continues.
In this thesis, implementation of a jitter measurement infrastructure IP (IIP) is presented. We use FPGA to realize the jitter measurement technique reported in [6]. The BIST technique in [6] measures the RMS value of a Gaussian distribution period jitter. We choose to implement the technique with FPGA because it offers great potential of reuse. With the increasing availability of embedded FPGA, one may program the FPGA to be a jitter measurement circuit, which can be reprogrammed to the desired mission mode function after the jitter measurement is finished. This way, the hardware overhead is minimized.
Finally, to realize a jitter source based on the amplitude to phase conversion method, the AWG (arbitrary waveform generator) Teckronix-AWG520 is employed (RMS jitter: max 668.5 ps and 100Mhz). The jittered signals are applied to the IIP and the measurement results. According to the experimental results, the IIP measure range is 250 ~ 500 ps when the error is less than 10%.
Subjects
智產權
可程式邏輯閘陣列
時脈抖動
FPGA
IP
clock jitter
Type
thesis
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