Delta-Sigma Time-to-Digital Converters for Low Power Applications

The thesis presents low power design techniques for delta-sigma time-to-digital (TDC) converters. By using time register to transfer the time-domain quantization error, the resolution of the TDC can be improved due to noise-shaping of the quantization error. Fabricated in 90-nm CMOS, the first-order delta-sigma TDC consumes a current of 5 uA from a 0.3-V supply. The circuit demonstrates an equivalent number of bits (ENOB) of 10.9 bits in 50 kHz signal bandwidth. Moreover, a capacitance-to-digital (CDC) converter with a second-order delta-sigma TDC is also presented. Consuming 18.4 uA from a 0.6-V supply, the second-order CDC achieves an ENOB of 9.8 bits in 2 kHz signal bandwidth with an input capacitance range of 5 pF.