A CMOS square-Law vector summation circuit
Journal
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
Journal Volume
43
Journal Issue
7
Pages
520-524
Date Issued
1996
Author(s)
Abstract
A CMOS vector summation circuit using the square-law characteristics of MOS transistors in the saturation region is presented. Simulation and experimental results are given to verify the theoretical analyzes. Second-order effects such as mobility reduction and transistor mismatch are also investigated. The proposed circuits are expected to be useful in analog signal-processing applications.
SDGs
Type
journal article