A real-time programmable LDPC decoder chip for arbitrary QC-LDPC parity check matrices
Journal
2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009
Pages
369-372
Date Issued
2009
Author(s)
Abstract
For the applications of next-generation channel-adaptive communication systems, a real-time programmable LDPC decoder architecture is proposed with three design techniques: divided-group comparison (DGC), adaptive wordlength assignment (AWA), and efficient early termination scheme (EETS). By utilizing programmable principle, the hardware architecture can support arbitrary Quasi-Cyclic LDPC parity check matrices, including various locations of 1's, information bits, codeword lengths, and code rates. The prototyping LDPC decoder chip using 0.13um CMOS technology, which supports up to 23 code rates with a maximum block size of 1536 bits, only occupies 4.94 mm 2 die area, operates at 125 MHz, and dissipates 58 mW power.
Type
conference paper